Dissertation Defense Schedule
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PROGRAM | Electrical & Computer Engineering
Dataflow Software Pipelining for Codelet Model using Hardware-Software Co-design
Software pipelining is a code mapping scheme to exploit pipelined parallelism in a loop. It has been successfully applied by compilers to exploit Instruction Level Parallelism (ILP), capable of scheduling up to a couple of hundreds of machine instructions in pipelined execution. However, rapid advances in chip technology and computer architecture have enabled the design and production of chips with thousands of cores or even hundreds of thousands of cores, far beyond the limit of classical software pipelining. An open question is: Can the software pipeline technology be extended and applied to meet such challenges?
This work addresses the above challenges by extending the software pipelining beyond the limit of fine-grain, instruction-level parallelism for the Codelet Model.
The extended operational semantics of the Codelet model takes advantage of dataflow software pipelining principles by exploiting pipelined parallelism across loops (coarse-grain) using single owner FIFO buffers across Codelet’s dependencies. Extended Codelet Abstract Machine (xCAM) and Local Codelet Core Memory (LCCM) enables efficient implementation of FIFO buffers based hardware-software co-design principles.
These extensions are realized on Intel GPU which is a base architectures for one of the exascale supercomputers using OpenCL programming model. The Codelet Pipe and its Application Programming Interface (API) not only addresses the challenge of programmability but also allow users to exploit hardware-software co-design using a novel architectural feature like Shared Local Memory.
We use the Cannons algorithm for matrix multiplication to study the performance implications of the extended Codelet Model. We evaluate Codelet Pipe using micro-benchmarks to provide further insights into performance.