This event is for undergraduate and graduate students looking to network with major companies in the computer science industry. Be sure to stop by and bring your resume! You can find more info in the events tab.
Quick Facts: Vanguard will be on campus October 10 to conduct interviews. The last day to submit your resume is September 28.
CISters co-sponsored this event with the ACM.
Attendees learned a lot of hints about how to prepare for the September 26 Job Jamboree from UD alumni Chris Fahey, Kevin Owocki, and Tara Strobel, now at Vanguard.
There were plenty of opportunities to have questions answered.
Some important things we learned:
- Give your cover letter and resume to the same company multiple ways in multiple forms to the interviewers, technical staff, HR, the web site. You don’t want your resume to slip through the cracks; the more people who know your name, the better.
- Bring multiple copies of your resume to the Job Jamboree and similar fairs.
- Sell yourself as someone who can help the company. On the first interview, don’t talk about salary, bonuses, etc., because that’s how the company benefits you.
- In the interview, if you’re asked what your greatest weakness is, turn it into a positive.
- If you’re asked about group/team or leadership experiences, you don’t necessarily only have to talk about academic or coding projects. You can talk about sports teams or other extracurricular experiences, which also show that you’re well-rounded.
Article by Diane Kukich / UDaily link.
UD group for women in technology becomes official ACM-W student chapter
CISTERS, a group that brings together women in technology-driven fields at the University of Delaware, has become an official ACM-W student chapter.
A sub-group of the Association of Computing Machinery, ACM-W celebrates, supports, and advocates for women in computing, providing a wide range of programs and services and working in the larger community to advance the contributions of technical women.
“CISTERS becoming an ACM-W Chapter formally connects UD students with the national organization and other ACM-W chapters in the region as well as globally,” says Lori Pollock, professor of computer and information sciences, who is serving as adviser to the chapter. “This connection will provide support in various ways, including, for instance, a distinguished lectureship program, which will pay for the travel of speakers to campus.”
“It’s important for the small group of women in computing here on campus to feel part of a bigger organization that has the same mission and can provide support and a feeling of connection with other groups at other universities across the world,” she adds.
Preetha Chatterjee, a doctoral student in computer science and chair of the UD chapter, points out that members have the opportunity to gain technical, communication, teamwork, problem-solving and leadership skills through their volunteer activities with the organization. The group also hosts a book club and career and networking events.
“The organization is open to all undergraduate, graduate, and faculty in technology-driven fields, not just computer and information sciences,” she says. “Our goal is to promote women in technology at UD and have fun.”
Benefits of affiliation with the national organization include a three-month complimentary electronic subscription to Communications of the ACM; a full-year subscription to Crossroads, ACM’s student magazine; TechNews, a tri-weekly technical news service; CareerNews, an email newsletter filled with industry tips, trends and insights; and MemberNet, the ACM member newsletter.
Upcoming CISTERS events include the following:
• Oct. 13: Book Club series, first meeting.
• Nov. 15: Book Club Series, second meeting.
• Dec 5: Technical talk in collaboration with the Bioinformatics Student Association.
Scaling Up Next Generation Supercomputers
- Date and Time: Wednesday February 4, 2009 – 3:15PM-4:15PM
- Room: Gore Hall 116
- Contact: Michela Taufer (firstname.lastname@example.org)
Historically, technology has been the main driver of computer performance. For many system generations, CMOS scaling has been leveraged to increase clock speed and build increasingly complex microarchitectures. As technology-driven performance gains are becoming increasingly harder to achieve, innovative system architecture must step in. In the context of the design of the Blue Gene/P supercomputer chip, we will discuss how we adopted a holistic approach to optimization of the entire hardware and software stack for a range of metrics: performance, power, power/performance, reliability and ease of use. The new Blue Gene/P chip multiprocessor (CMP) scales node performance using a multi-core system-on-a-chip design. While in the past large symmetric multi processor (SMP) designs were sized to handle large amounts of coherence traffic, many modern CMP designs find this cost prohibitive in terms of area, power dissipation, and design complexity. As multi-core processors evolve to larger configurations, the performance loss due to handling coherence traffic must be carefully managed. Thus, to ensure high efficiency of each quad-processor node in Blue Gene/P, taming the cost of coherence of traditional SMP designs was a key requirement.
The new Blue Gene/P chip multiprocessor exploits a novel way of reducing coherence cost by filtering useless coherence actions. Each processor core is paired with a snoop filter which identifies and discards unnecessary coherence requests before they can reach the processor cores. Removing unnecessary lookups reduces the interference of invalidate requests with L1 data cache accesses, and reduces power by eliminating expensive tag array accesses. This approach results in improved power and performance characteristics.
To optimize application performance, we exploit parallelism at multiple levels: at the process-level, thread-level, data-level, and instruction-level. Hardware supported coherence allows applications to efficiently share data between threads on different processors for thread-level parallelism, while the dual floating point unit and the dual-issue out-of-order PowerPC450 processor core exploit data and instruction level parallelism, respectively. To exploit process-level parallelism, special emphasis was put on efficient communication primitives by including hardware support for the MPI protocol, such as low latency barriers, and five highly optimized communication networks. A new high performance DMA unit supports high throughput data transfers.
As the result of this deliberate design for scalability approach, Blue Gene supercomputers offer unprecedented scalability, in some cases by orders of magnitude, to a wide range of scientific applications. A broad range of scientific applications on Blue Gene supercomputers have advanced scientific discovery, which is the real merit and ultimate measure of success of the Blue Gene system family.
Valentina Salapura is an IBM Master Inventor and System Architect at the IBM T.J. Watson Research Center. Dr. Salapura has been a technical leader for the Blue Gene program since its inception. She has contributed to the architecture and implementation of several generations of Blue Gene Systems focusing on multiprocessor interconnect and synchronization and multithreaded, multicore architecture design and evaluation. Most recently, she has been unit lead for several units of Blue Gene/P, as well as a leader of the chip and system bringup effort. Valentina Salapura is recipient of the 2006 ACM Gordon Bell Prize for Special Achievements for the Blue Gene/L supercomputer and Quantum Chromodynamics. Dr. Salapura has received several corporate awards for her technical contributions. Dr. Salapura is the author of over 60 papers on processor architecture and high-performance computing, and holds many patents in this area. Dr. Salapura is an ACM Distinguished Speaker and a Senior Member of the IEEE.